This invention relates to a unique receiver processor system that improves the signal-to-noise ratio (SNR) of received signals. Unlike conventional receiver systems, a system utilizing the method in accordance with the present invention realizes a reduction in the affects of all types of noise, including but not limited to thermal noise. There are few communications systems, if any, that would not benefit from a significant reduction in the inherent thermal noise resulting from the necessary amplification practices employed in most of these type systems. All types of noise, whether it is noise received by the receiver along with the intended signal, such as in the form of interfering signals, or noise generated within the receiver system after the signal has been received, limit the ability of the receiver system to identify weak signals and distinguish them from their stronger counterparts.
Thermal noise, which is basically caused by thermal agitation of electrons in a conductor, is introduced into a receive system as a result of necessary amplification processes within the system. This type of noise is typically a limiting factor in regard to the ability of the system to identify a weak signal. When such noise is substantially reduced, a potential results for improving the receptivity of the signal, thus, also enabling tradeoffs in parameters, such as bandwidth and those typically involved in various multiplexing techniques. That is, as noise is reduced, weaker signals can be detected more reliably and a lower error rate can be achieved. After an acceptable error rate is achieved, the improvement in signal-to-noise ratio (SNR) can be parlayed into an increase in the number of signals that can be multiplexed within the system, while maintaining the same error rate; thereby increasing the signal capacity of the system.
The invention disclosed herein includes methods and corresponding system architecture that enables relatively weak signals to be readily identified by increasing the SNR of the receive system. Further, a system in accordance with the present invention can be implemented in hardware, software or a combination of both hardware and software. As will become apparent to those of skill in the art after reviewing the following disclosure, implementation of the methods and systems disclosed herein increase channel capacity of the system and improve other parameters associated with receive system performance.
More particularly, the present invention improves upon, as well as provides a unique implementation of, the iterative noise reduction processes disclosed in previous U.S. patents and published applications assigned to the current assignee of the present invention, Apex/Eclipse Systems, Inc., e.g., U.S. Pat. Nos. 7,076,227 and 7,106,853, the contents of which are incorporated herein in their entirety for all that they disclose.
Specifically, in comparison to the processing techniques disclosed and claimed in the previously issued wireless and wire-line patents and applications identified above, in accordance with the present invention the Topological Number Array (TNA) has been essentially eliminated to reduce the complexity of the processing. The notion of iterative processing was retained, but instead of operating on addresses within the TNA, according to the prior techniques, the input samples are operated upon to compute the noise estimate.
Furthermore, according to the present invention the selection of a surrogate probe and a first noise probe includes utilizing the average of input samples surrounding the input being processed. This average value is then used to select coefficients for computing the two types of probes.
According to the present invention, an improved method including, for example, implementation of one or more of the specific methods disclosed herein, which are ideally implemented in a digital system, is applied to a received signal immediately after analog-to-digital conversion (ADC) of the receive signal has occurred. In accordance with one exemplary embodiment of the invention, the method(s) are implemented in custom semiconductor gate arrays and/or programmable gate arrays.
As will become more apparent through examination of at least one example provided in detail below, one aspect of the invention includes the use of numerical logic and the relationship of various equations to quantify different functions. Methods according to the invention utilize the analysis of numerical actions to determine subsequent steps in an iterative process. Specifically, according to one or more embodiments of the invention, an estimate of a noise component of an input signal is determined and this estimated noise value is removed from the original input sample to provide an enhanced signal for subsequent signal processing.